Recently, wall television sets using a thin plasma display panel (hereinafter referred to as a “PDP”) having a wide screen have been attracting much attention. FIG. 25 is a block diagram schematically showing the structure of a PDP driver for driving a PDP.
For the sake of simplicity, an exemplary PDP 700 having two electrodes is illustrated in FIG. 25. The PDP 700 includes a plurality of scan driver ICs (integrated circuits) 800-1, 800-2, 800-3, . . . , and 800-k, and also data (address) driver ICs 900-1, 900-2, 900-3, . . . , and 900-m. (Here k and m are arbitrary numbers.)
The scan driver ICs 800-1, 800-2, 800-3, . . . , and 800-k drive respective multiple scanning and holding electrodes 911. The data (address) driver ICs 900-1, 900-2, 900-3, . . . , and 900-m drive respective multiple data electrodes 912 corresponding to the respective colors R (red), G (green), and B (blue). The scanning and holding electrodes 911 and the data electrodes 912 are extended perpendicularly to each other such that a lattice is formed and discharge cells (not shown) are arranged at the cross points of the electrodes 911 and 912.
If each scan driver IC 800-1, 800-2, 800-3, . . . , or 800-k is capable of driving 64 scanning and holding electrodes 911, the number k will be 12 for the extended video graphic array (XGA), since the PDP 700 has 1024×768 pixels.
For displaying images, data is written to the discharge cells from data electrodes 912 by scan driver ICs 800-1 through 800-k and data driver ICs 900-1 through 900-m and by scanning the scanning and holding electrodes 911 (address discharge period) and the discharge in the discharge cells is maintained by outputting holding pulses several times to the scanning and holding electrodes 911 (discharge holding period).
Now the structure of the conventional scan driver IC (hereinafter referred to as the “display device driver circuit” or simply as the “display driver”) will be described below. FIG. 26 is a block diagram of a conventional display device driver circuit.
Referring now to FIG. 26, the conventional display driver 800 includes shift registers 810-1 through 810-n, data selectors 820-1 through 820-n, and output stage circuits 830-1 through 830-n. The shift registers 810-1, 810-2, 810-3, . . . , and 810-n convert the serial signals inputted via a terminal DATA for controlling the scanning and holding electrodes 911 to parallel signals in synchronism with a clock signal inputted to a terminal CLK. The data selectors 820-1, 820-2, 820-3, . . . , and 820-n send the signals transferred bit by bit from the shift registers 810-1, 810-2, 810-3, . . . , and 810-n to the output stage circuits 830-1, 830-2, 830-3, . . . , and 830-n. Here, n is an arbitrary number, which, for example, is 64 for the 64 bits display driver 800. The display driver 800 drives 64 scanning and holding electrodes 911. A terminal SH and a terminal SL are connected to the data selectors 820-1, 820-2, 820-3, . . . , and 820-n. An all-the-outputs H-level-fixing signal for fixing all the scanning and holding electrodes 911 at an H (high) level is inputted to the terminal SH. An all-the-outputs L-level-fixing signal for fixing all the scanning and holding electrodes 911 at an L (low) level is inputted to the terminal SL.
FIG. 27 is a block circuit diagram of the conventional output stage circuit in the display driver for driving the PDP. Referring now to FIG. 27, the output stage circuit 830 includes a level shifter circuit 831, inverters 832 and 833, a buffer circuit 834, and two insulated gate bipolar transistors (IGBTs) 835 and 836 capable of making a high current flow across a unit area.
The level shifter circuit 831 is formed of p-channel MOSFETs (p-channel metal oxide semiconductor field effect transistors: hereinafter referred to as “PMOSs”) 831a and 831b exhibiting a high breakdown voltage; and n-channel MOSFETs (hereinafter referred to as “NMOSs”) 831c and 831d. The source terminal of the PMOS 831a is connected to a high voltage supply terminal VDH that feeds a voltage between 0 V and a VDH level (100 V). The drain terminal of the PMOS 831a is connected to the drain terminal of the NMOS 831c, the gate terminal of the PMOS 831b, and the gate terminal of the IGBT 836. The gate terminal of the PMOS 831a is connected to the drain terminal of the PMOS 831b and the drain terminal of the NMOS 831d. The source terminal of the PMOS 831b is connected to a high voltage supply terminal VDH. The drain terminal of the PMOS 831b is connected to the drain terminal of the NMOS 831d and the gate terminal of the PMOS 831a. The gate terminal of the PMOS 831b is connected to the drain terminal of the PMOS 831a. The source terminals of the NMOSs 831c and 831d are grounded. The signal inputted from an input terminal IN (the signal outputted from any of the data selectors 820-1 through 820-n) is inputted to the gate terminal of the NMOS 831c via the inverter 832, and is inputted to the gate terminal of the NMOS 831d via the inverters 832 and 833.
The buffer circuit 834 inverts the level of the signal inputted from the input terminal IN via the inverters 832 and 833, and inputs the signal with the level thereof inverted to the gate terminal of the IGBT 835. The collector terminal of the IGBT 836 is connected to the high voltage supply terminal VDH. The emitter terminal of the IGBT 836 is connected to an output terminal DO and the collector terminal of the IGBT 835. The emitter terminal of the IGBT 835 is grounded.
The output terminal DO is connected to the scanning and holding electrodes 911 shown in FIG. 25 and further to the discharge cells (regarded as capacitance). The operations of the output stage circuit 830 are described below with reference to a timing chart.
In the following, the voltage of 100 V will be sometimes referred to as the “VDH level” and the voltage of 5 V as the “VDL level”. FIG. 28 is a timing chart illustrating the operations of the conventional output stage circuit.
In FIG. 25, the voltage waveforms of the input signal inputted to the input terminal IN, the gate signals of the NMOSs 831c and 831d, and the gate signals of the IGBTs 835 and 836 are shown. Also shown are the voltage waveforms of the output signal from the output terminal DO.
As an input signal of 5 V (the VDL level) is inputted to the input terminal IN (at the time t10), setting the input terminal IN at the H level, the gate signal of the NMOS 831c is set at the L level, turning off the NMOS 831c. The gate signal of the NMOS 831d is set at the H level, turning on the NMOS 831d. As a result, the PMOS 831a is turned on, setting the gate signal of the IGBT 836 at 100 V. The IGBT 836, with the gate signal thereof set at 100 V, is turned on, outputting the output voltage of 100 V to the output terminal DO. Since the gate signal of the IGBT 835 is at the L level (GND (0 V)) in FIG. 28 at this time, the IGBT 835 is turned off. (In the following descriptions, the L level is GND, that is 0 V.)
As the input signal shifts to the L level (at the time t11), the gate signal of the NMOS 831c in the level shifter circuit 831 is set at the H level, turning on the NMOS 831c, and the gate signal of the NMOS 831d is set at the L level, turning off the NMOS 831d. As a result, the PMOS 831a is turned off and the PMOS 831b is turned on. As a result, the gate signal of the IGBT 836 is set at the L level, turning off the IGBT 836. Since the gate signal inputted to the gate terminal of the IGBT 835 is set at the H level, the IGBT 835 is turned on and the output signal outputted from the output terminal DO falls to 0 V.
An improved conventional output stage circuit is disclosed in JP PHei.11(1999)-98000A (Paragraphs [0019] through [0023], FIGS. 1 and 2). The improved conventional output stage circuit disclosed in this patent publication slows down the rise of the output signal thereof (the current that the output stage circuit feeds) by clamping the voltage between the gate and the source of the FET connected between the high voltage supply terminal and the output terminal of the output stage for a certain period during the switching for preventing the noises due to too fast rise of the output signal thereof from causing device breakdown. JP P2001-134230A (FIG. 1) discloses a technique for obtaining a sufficient current driving capability even when the transistor connected between the output terminal and the reference voltage supply terminal is minimized to reduce the chip size.
FIG. 29 is a block circuit diagram of the other conventional output stage circuit in the display driver for driving the PDP. The output stage circuit 840 in FIG. 29 includes, in the same manner as the output stage circuit 830 in FIG. 27 does, a level shifter circuit 831 and IGBTs 835 and 836.
A Zener diode 844 and resistance 845 are connected between the gate and the emitter of the IGBT 836 connected to the high voltage supply terminal VDH. The Zener diode 844 is connected to prevent a voltage exceeding the breakdown voltage between the gate and the emitter of the IGBT 836 from being applied between the gate and the emitter of the IGBT 836. The resistance 845 is connected to boost the gate potential to the VDL level (5 V). Since a high voltage is not applied between the gate and the emitter of the IGBT 836 due to the Zener diode 844, the gate oxide film of the IGBT 836 in FIG. 29 may be formed to be thinner than the gate oxide film of the IGBT 836 in FIG. 27, and to be as thin as the gate oxide film of the IGBT 835. When the output stage circuit does not include any Zener diode 844 or resistance 845 as shown in FIG. 27, and therefore the gate oxide film of the IGBT 836 is thick, it is necessary to add a step for thickening the gate oxide film of the IGBT 836. If the gate oxide film of the IGBT 836 is formed at the same thickness as the gate oxide film thickness of the PMOSs 831a and 831b exhibiting a high breakdown voltage in the same manner as the IGBT 836, it will be necessary to enlarge the PMOSs 831a and 831b. However, when the Zener diode 844 and the resistance 845 are disposed as shown in FIG. 29, it becomes possible to form the gate oxide films of the IGBTs 836 and 835 at the same thickness. Therefore, the provision of the Zener diode 844 and the resistance 845 facilitates manufacturing the output stage circuit without either adding the step for thickening the gate oxide film of the IGBT 836 or widening the areas of the PMOSs 831a and 831b. An example of the output stage circuit 840 as described above is disclosed in JP P2000-164730A (FIG. 1).
The output stage circuit 840 operates in the same manner as the output stage circuit 830 illustrated in FIG. 27. The wiring pattern in the conventional display driver and the mounting thereof on a circuit board are described in detail in JP P2002-341785A.
When the output terminals DO1 through DOn in the conventional display driver are short-circuited by metal filings and other such foreign materials, an overcurrent is caused in connecting the power supply or during the operation. This further causes breakdown of the devices (IGBTs).
If the current density of the IGBTs is reduced so as not to cause breakdown of the IGBTs even when the caused short circuit continues for a long time, larger IGBTs will be needed for obtaining a current as high as necessary. These problems are caused also in driving flat panel display devices other than PDPs, such as liquid crystal displays and EL (electro-luminescent) displays.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a display device driver circuit that facilitates preventing the constituent IGBTs from being broken down even when the output terminals thereof are short-circuited.